Feature Architectures for Multi - Gigabit Wire - Linked Clock and Data Recovery Ming - ta Hsieh and Gerald

نویسنده

  • Gerald E. Sobelman
چکیده

Clock and data recovery (CDR) architectures used in highspeed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized. © photo f/x 2 FOURTH qUaRTeR 2008 1531-636X/08/$25.00©2008 Ieee Ieee CIRCUITs anD sysTems magazIne 45 Authorized licensed use limited to: Texas A M University. Downloaded on January 16, 2009 at 19:57 from IEEE Xplore. Restrictions apply. 46 Ieee CIRCUITs anD sysTems magazIne FOURTH qUaRTeR 2008 A clock and data recovery (CDR) circuit is an essential block in many high-speed wire-linked data transmission applications such as optical communications systems, backplane data-link routing and chip-to-chip interconnection. The important role of a CDR is to extract the transmitted data sequence from the distorted received signal and to recover the associated clock timing information. Figure 2 illustrates a simplified functional diagram of clock recovery and data retiming using a CDR circuit. The clock recovery circuit detects the transitions in the received data and generates a periodic clock. The decision circuit often uses D-type Flip-Flops (DFFs) driven by the recovered clock to retime the received data, which samples noisy data and then regenerates it with less jitter and skew [2]. A generic block diagram of a high-speed wire-linked data transmission system is shown in Figure 3, where the received data is equalized in the receiver input buffer and retimed in the CDR module before proceeding into the deserializer module. A source-asynchronous system is shown, in which the transmitting and receiving sides use different clock sources. This results in a possible a frequency offset between the transmitted data and the local clock on the receiver side due to natural device mismatches, creating additional challenges for the CDR circuit. Most wirelinked communication systems fall into this category. In contrast to this, data transmission systems such as chip-to-chip interconnect in which both the transmitter and receiver use the same clock source are known M.-t. Hsieh and G.E. Sobelman are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 (E-mail: [email protected]). 140

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تاریخ انتشار 2009